Archive for September, 2011

I’m going to be rich!!!

In the fall of 2010, while completing my bachelor’s senior project, I accidentally designed a helicopter that flies without its rotors moving!  I’m going to make billions!

Using HDL the Right Way

For digital design, the fastest way to design a circuit is using a hardware description language (HDL).  All HDLs have one common flaw, they have constructs and syntax that do NOT describe hardware.  This causes fundamental issues for engineers designing ASICs, FPGAs, CPLDs, etc.

To overcome the fundamental problem with HDLs, I propose a few simple steps to allow designers to write code that translates to optimally synthesized logic.  The steps are:

1.  Use an HDL to describe the hardware.

The key word in “hardware description language” is description.  HDLs should be used to describe a digital circuit.  Unfortunately engineers often use an HDL to create a circuit that were it not for the synthesizer they would have no idea how to design it.  This almost always results in a sub-optimal design.  If you don’t know how to make a circuit, why should the synthesizer?

Before writing any HDL code, you should sit down and either make a diagram or have a good mental view of the circuit you are trying to design.  Once you have this, you can use the HDL to syntactically describe the circuit.

2.  Use only HDL syntax that can directly synthesize to logic.

As mentioned earlier, HDLs contain syntax that doesn’t describe digital hardware.  Do not use these constructs.  Only use blatant hardware-based assignments and operators.  This will allow your synthesized design to follow closely to what is found in the HDL code.

Books like “The Designer’s Guide to VHDL” actually do the designer a disservice.  99% of this book talks about unsynthesizable code while the last 1% is useful synthesizable code.  Digital logic is very easy.  It doesn’t require many types of syntax.  Our digital design world would flow much better if HDLs were only designed to describe hardware.  The unfortunate fact that many HDLs have testbench-like syntax causes less-knowledgable designers to use these constructs out of ignorance.  This will undoubtedly burn them at some point in their career.

3.  Use a netlist viewer.

After designing a digital circuit using an HDL, synthesize it and use an RTL netlist viewer to verify that the synthesized design contains the proper logic.  This is critical!  Often times the synthesizer will not properly infer logic blocks.  Using a netlist viewer will allow you to double-check the synthesized results.  This will also help you find bugs in your code that may not have been syntax bugs.  Usually when a bug makes it through the synthesis stage, the result will be quite different from what you expected.  Using an RTL netlist viewer creates one more process step, but it will reduce your development time because you’ll find and correct problems in earlier stages.

For you FPGA and CPLD designers, using a technology netlist viewer will give you yet another verification step.  This is very useful when you are using an HDL to describe some device primitive such as block RAMs, clock muxes, tristate drivers, dual-data registers, digital signal processing (DSP) blocks, and many more.

4.  Do not use your hardware HDL for your testbench HDL.

This is a commonly debated topic.  I don’t think you absolutely have to follow my advice to produce good hardware, but I definitely think it makes it easier.  I believe that there is a fundamental problem with HDLs in that they attempt to satisfy the syntactical needs of hardware and testbenches.  This would be better off split into two languages.  Using the same language causes issues because if you made a logic mistake in your hardware, what makes you think you wouldn’t make the same or inverse mistake in your testbench?

For myself I have adopted a pretty simple strategy.  I write all my hardware code in VHDL or Verilog.  I only use basic hardware-like constructs and avoid any use of complex functions that have no simple hardware explanation.  For testing, I use SystemVerilog.  SystemVerilog provides a very cool interface between hardware and computer-language-like programmability.  The typical problem with creating testbenches is that you feel like you are creating another hardware suite.  Using SystemVerilog I create drivers which send and receive object-oriented data structures to and from my top-level hardware design.  These drivers have a hardware side that is attached to my hardware design.  They also have a programmable side which is attached to my testing logic.

Here is an example.  If my hardware design was an IP packet router, I would create a SystemVerilog class that represents an IP packet.  I can use computer-language-like programming to create and monitor the status of these packets.  From this programmable side, I send all the created packets to the driver.  The driver takes the data and communicates with my hardware unit over the physical protocol defined by the hardware.  I would also have a driver for receiving packets.  After all is said and done, I can use typical C++ like programming to verify proper IP routing of my hardware device.  Simple, right?

Examples of what NOT to do:

Example #1:

It is common in communication systems to send a known pattern of bits at the beginning of each frame so that the receiving side can synchronize itself to the bit stream. For communication systems, you often need to be tolerant of a few bits errors.  To search for the sync bits, you just need to XOR the last received bits with the known sync pattern then count the number of ones, which is the number of errors.  For counting the post-XOR ones, I often see a VHDL function declared like this:

function count_ones (a : std_logic_vector) return unsigned is
  variable b : unsigned(log(a'length) downto 0) := (others => '0');
  for i in a'range loop
    if (a(i) = '1') then
      b := b + 1;
    end if;
  end loop;
  return b;

This may look harmless, but try to think of what kind of hardware it will make. All the synthesizers I’ve tried this on make an a’length series sequence of b’length adders.  Obviously this produces absolutely horrible timing results.  There are better ways to count ones.  Don’t get stuck with a sequences of adders.

Example #2:

Back when I was a digital design rookie, I was trying to figure out how to take a binary number and produce a sequence of BCD values.  For example 10100010(162) would convert to 0001(1), 0110(6), 0010(2).  I found a commonly known algorithm for this.  The 8-bit algorithm is:

1.  If any column (100’s, 10’s, 1’s, etc.) is 5 or greater, add 3 to that column.
2.  Shift all #’s to the left 1 position.
3.  If 8 shifts have been performed, it’s done! Evaluate each column for the BCD values.
4.  Go to step 1.

I then attempted to translate this into hardware.  I wanted a completely combinational implementation for single clock latency.  This is what I naively produced:

module bcd (
    input [7:0] binary,
    output reg [3:0] hundreds,
    output reg [3:0] tens,
    output reg [3:0] ones);

    integer i;
    always @(binary) begin
        // set 100's, 10's, and 1's to zero
        hundreds = 4'd0;
        tens = 4'd0;
        ones = 4'd0;

        // loop 8 times
        for (i=7; i>=0; i=i-1) begin
            // add 3 to columns >= 5
            if (hundreds >= 5)
                hundreds = hundreds + 3;
            if (tens >= 5)
                tens = tens + 3;
            if (ones >= 5)
                ones = ones + 3;

            // shift left one
            hundreds = hundreds << 1;
            hundreds[0] = tens[3];
            tens = tens << 1;
            tens[0] = ones[3];
            ones = ones << 1;
            ones[0] = binary[i];

Yes, I know, there numerous issues in this code. Can anyone look at this code and figure out what it will make?  I can’t!  Even though this code properly produces the BCD sequence, it produces a very large combinational path.  Don’t use it!

Multiplex EasyStar Airplane


In anticipation of developing a quadcopter, I bought a Spektrum Dx5e/AR500 transmitter/receiver pair.  Knowing that the quadcopter would probably take many months to design and build, my wife lovingly thought to buy me an RC Airplane to hold me over until I finished my quadcopter.  She snooped on my computer and found that I had been looking at the Multiplex EasyStar.

The version I got (linked below) didn’t come with an Tx/Rx, servos, ESC, or battery.  I jumped on and bought two servos, a 2-cell lipo battery, and a cheap brushed ESC.  It turned out that the servos I bought were a low-voltage version and very weak.  Because I didn’t want to wait for another shipment from China, I ordered some better servos from

My final parts list became:

Total: $216

First Flight:

My first flight went horribly!  I was too anxious to fly and didn’t wait for a good day.  Let’s just say I flew around for a few minutes with completely no control and then ended my performance with a full throttle nose dive into the ground.  The cockpit area of the fuselage broke in half.  To those of you reading this deciding whether to get into RC planes or not, don’t let this discourage you.  I did EVERYTHING wrong.  Not only was I too anxious, but I was also nervous.  I left the throttle at full.  This was a bad combination.

I fixed the fuselage using the same glue I put it together with and some clear box tape.  It actually seemed to get even stronger!  I waited for a calm day then attempted flight number two.  I remembered to stay clam, set the throttle to full, hand launched, got control, then set the throttle to about half.  I couldn’t believe how easy it was to fly!  I was flying around with perfect control in no time.  I even got brave and applied full throttle and pulled off a loop.  It was ridiculously fun!  Then I realized I needed to land sometime soon or it would land by itself (another nose dive into the ground?).  Once I got close to the ground, I cut the throttle to about 1/4 power then slowly descended in a straight line.  It smoothly slid across the grass until it stopped!

Aggressive Flight Modification:

After a few flights, I determined that the aircraft was a bit sluggish when looping and turning.  I decided to do a few things to fix this:

  • Servo Cable Adjustment:
    Each servo cable attaches to the corresponding flap using a threaded clamp that sits in one of three slots.  When I first put the airplane together, I put the clamp in the least aggressive slot (furthest from the flap).  I just moved all the clamps to the most aggressive location (closest to the flaps).  This increased the aggressiveness of the aircraft dramatically.
  • Rudder Enhancement:
    Unlike a typical RC airplane, the rudder on the EasyStar controls the tail and the roll of the aircraft.  Its design is far too small for its purpose.  I used some thin, stiff cardboard and super glue to extend the length of the rudder.  The stock length is about 1″.  I modified it to be about 6″.  This turned out to be too much rudder when the aircraft was moving quickly.  I cut the extended flap down to about 3.5″.  It now works great.  The plane now responds very fast but I also don’t get out of control when I am moving quickly through a turn.


This airplane is super durable.  I have crashed in one way or another numerous times!  Most of the time nothing happens.  I’m pretty sure my fuselage is now 40% glue, 45% tape, and 5% foam.  It still flys like a champ!  The location of the propeller is perfect for beginners.  It has never been harmed in all my crashes.

Too Aggressive?:

Apparently my modification makes the aircraft more aggressive than the foam wings can handle.  To get enough speed for the many tricks I’ve learned, I take the EasyStar up as high as I can while still feeling comfortable, then dive nose down.  Sometimes I just do this to see how fast I can get going and how close I can get to the ground until I pull up.  Each time I do this I can see the wings flexing back.  One day my dives were getting really fast and one of the wings finally gave out.  The wing snapped in half and the rest of the plane went spinning into the ground.  I could probably beef up the wing strength with some carbon fiber rods, however, $25 for new wings isn’t too much to ask for 6 months of abuse.

Verilog vs. VHDL

When it comes to Hardware Description Languages (HDLs), the two giants in industry are Verilog and VHDL.  These two languages are vastly different and both provide ample advantages and disadvantages.  Here I’ll show what I think are the pros and cons to these languages.  Since I am a hardware design engineer, I’ll only speak to the synthesizable aspects to the two languages.

My Verilog History:
While plugging away at a Computer Engineering degree at the University of Utah, I was introduced to Verilog for digital circuit design.  At first, I struggled to comprehend Verilog.  I was proficient with C, C++, and Java, so the syntax was familiar but seemed to have odd differences that bothered me.  Once I got the hang of it, Verilog became very powerful in my hands.  I grasped a hold of digital design and completed numerous projects in the FPGA world.  The crux of my Verilog experience was a hand crafted 32-bit RISC processor design.  Through all these experiences I learned to ignore the annoyances of Verilog and hack around them.

Verilog Likes:
To a C, C++, C#, or Java programmer, Verilog syntax will make you feel right at home.  The constructs, operators, and numerical logic follows very closely with C.

Verilog Dislikes:
Verilog was syntactically designed after C.  C is a great software language, however, as one of my professors once said “C is a loaded gun aimed at your foot!”.  The lack of type enforcement is what makes C super fast and super scary.  Without dealing with type checking, compiled C code is very efficient.  For most developers, this also causes buggy code.  Fortunately, software is easy to debug.  Like C, Verilog has weak type enforcement.  Along the same lines, Verilog also doesn’t enforce equal sized bit widths for assignments, operations, and comparisons.  Unlike software, hardware isn’t faster when type checking is ignored.  I can’t tell you how many times a lack of type checking and/or width checking has burned me while designing hardware in Verilog!

My VHDL History:
After graduation I found employment with L-3 Communications in the Advanced Networking Hardware design group.  Due to legacy government contracts, L-3 has adopted VHDL as the HDL of choice.  Although I landed an absolutely awesome job, the thought of designing logic in a language that was derived from ADA gave me a sour taste.  As I begun a few projects, VHDL really annoyed me.  It seemed like I was typing the same thing over and over and over.  I realized that 100 lines of good Verilog translates to 300 lines of good VHDL.  As time went on I discovered the true power of VHDL.

VHDL Likes:
VHDL is inherently safe.  It basically has no primitive data types.  All data types are tied to some library which defines all operations.  Users can create their own data types and operators.  For synthesizable hardware this isn’t super useful however every state machine is best designed using a custom type.  Each time an operator is used, the corresponding function is called.  No automatic conversions are ever made.  You can’t accidentally get something you weren’t expecting.  VHDL is meticulously safe!  Along with being safe, the verbosity adds a level of confidence that what you are coding is what you’d expect.  For instance, the clock and reset structure for a ‘process’ is much better designed than ‘always’ blocks in Verilog.

VHDL Dislikes:
There are many little nuisances  in VHDL.  VHDL-2008 solves many of these nuisances but industry leading tools are not yet supporting the full VHDL-2008 standard.  Even though VHDL in inherently safe, older libraries and bad coding styles can still cause unwanted synthesis results.  VHDL considers all signals to be the same whether registered or not.  I like how Verilog has ‘reg’ and ‘wire’.  VHDL doesn’t have something like this.  I like to know just by seeing the declaration if it is a register or not.

The Winner Is…
After developing in both languages quite thoroughly, I choose VHDL as the best language for synthesizable logic.  The biggest reasoning for this is the safety aspect.  When it comes to hardware, it needs to have a blatant underlying implementation.  All arithmetic and comparisons should have obvious results.

Suggested Coding Standards:
There are several coding standards I live by to make VHDL a powerful language.  Before you criticize the guidelines, thoroughly think of the benefits they provide.  The rules are  here.